This invention relates generally to computer memory, and more particularly to systems and methods for providing a distributed memory controller that is independent of a particular memory technology.
Contemporary high performance computing main memory systems are generally composed of one or more dynamic random access memory (DRAM) devices, which are connected to one or more processors via one or more memory control elements. Overall computer system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor(s), any memory cache(s), the input/output (I/O) subsystem(s), the efficiency of the memory control function(s), the main memory device(s), and the type and structure of the memory interconnect interface(s).
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall system performance and density by improving the memory system/subsystem design and/or structure. High-availability systems present further challenges as related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems in regard to mean-time-between-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, etc. Other frequent customer requirements further exacerbate the memory system design challenges, and include such items as ease of upgrade and reduced system environmental impact (such as space, power and cooling).
FIG. 1 relates to U.S. Pat. No. 5,513,135 to Dell et al., of common assignment herewith, and depicts an early synchronous memory module. The memory module depicted in FIG. 1 is a dual in-line memory module (DIMM). This module is composed of synchronous DRAMs 8, buffer devices 12, an optimized pinout, and an interconnect and capacitive decoupling method to facilitate high performance operation. The patent also describes the use of clock re-drive on the module, using such devices as phase-locked loops (PLLs).
FIG. 2 relates to U.S. Pat. No. 6,173,382 to Dell et al., of common assignment herewith, and depicts a computer system 10 which includes a synchronous memory module 20 that is directly (i.e. point-to-point) connected to a memory controller 14 via a bus 40, and which further includes logic circuitry 24 (such as an application specific integrated circuit, or “ASIC”) that buffers, registers or otherwise acts on the address, data and control information that is received from the memory controller 14. The memory module 20 can be programmed to operate in a plurality of selectable or programmable modes by way of an independent bus, such as an inter-integrated circuit (12C) control bus 34, either as part of the memory initialization process or during normal operation. When utilized in applications requiring more than a single memory module connected directly to a memory controller, the patent notes that the resulting stubs can be minimized through the use of field-effect transistor (FET) switches to electrically disconnect modules from the bus.
Relative to U.S. Pat. No. 5,513,135, U.S. Pat. No. 6,173,382 further demonstrates the capability of integrating all of the defined functions (address, command, data, presence detect, etc) into a single device. The integration of functions is a common industry practice that is enabled by technology improvements and, in this case, enables additional module density and/or functionality.
FIG. 3, from U.S. Pat. No. 6,510,100 to Grundon et al., of common assignment herewith, depicts a simplified diagram and description of a memory system 10 that includes up to four registered DIMMs 40 on a traditional multi-drop stub bus. The subsystem includes a memory controller 20, an external clock buffer 30, registered DIMMs 40, an address bus 50, a control bus 60 and a data bus 70 with terminators 95 on the address bus 50 and the data bus 70. Although only a single memory channel is shown in FIG. 3, systems produced with these modules often included more than one discrete memory channel from the memory controller, with each of the memory channels operated singly (when a single channel was populated with modules) or in parallel (when two or more channels were populated with modules) to achieve the desired system functionality and/or performance.
FIG. 4, from U.S. Pat. No. 6,587,912 to Bonella et al., depicts a synchronous memory module 210 and system structure in which the repeater hubs 320 include local re-drive of the address, command and data to the local memory devices 301 and 302 via buses 321 and 322; generation of a local clock (as described in other figures and the patent text); and the re-driving of the appropriate memory interface signals to the next module or component in the system via bus 300.
In previous system structures, such as those described in the above references, maintaining the memory controller functions external to the processor chip made it possible to develop a relatively simple memory controller device to adapt any memory technology to the processor. This allowed the design of the processor to be completed relatively independently of the memory technology(ies) and gave the system designers the flexibility to match one or more of several processors to the a selected memory technology and/or subsystem for each of many targeted markets.
Due to the rapid increase in logic circuit capacity of silicon chips, most processor designs are now migrating to higher levels of integration, with an increasing percentage of the computer system elements being incorporated on the processor chip itself. The resulting processors will enable the construction of systems in which there are few, if any, external logic support chips required to build a computer system. This integration trend offers improved performance while reducing the cost, physical space, and power required for the overall computer system. One of the elements being migrated onto the processor chip(s) is the memory controller.
With the integration of the memory controller(s) into the processor(s), resulting systems will see improved performance due to the close proximity to the processor of the memory control function, the internal caches and the coherency buses. While this move is advantageous at a system level, it also results in a linkage of the processor to an individual memory technology or to a small subset of memory technologies. This linkage has the secondary effect of coupling the development and release of new memory products to the development and release of new processors. This coupling has caused problems in regard to the timing of computer system introductions to the optimum, cost-effective memory technology. For example, this coupling may result in systems that are closely linked to an emerging memory technology that has been modified, during development, to the point that it is no longer compatible with the processor, is being phased out due to the introduction of a more advanced technology, or is still an emerging technology which has not yet been broadly adopted (introducing cost and supply risk exposures).
Therefore, what is needed is the ability to distribute memory controller functions between a processor and a memory subsystem(s) in a manner such that the memory controller retains a close linkage to the internal coherency buses and cache structure of the processor, while eliminating the linkage to a specific memory technology.